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PIC18F2221/2321/4221/4321 FAMILY

DS39689F-page 34

2009 Microchip Technology Inc.

3.6.5.1

Compensating with the EUSART

An adjustment may be required when the EUSART

begins to generate framing errors or receives data with

errors while in Asynchronous mode. Framing errors

indicate that the device clock frequency is too high. To

adjust for this, decrement the value in OSCTUNE to

reduce the clock frequency. On the other hand, errors

in data may suggest that the clock speed is too low. To

compensate, increment OSCTUNE to increase the

clock frequency.

3.6.5.2

Compensating with the Timers

This technique compares device clock speed to some

reference clock. Two timers may be used; one timer is

clocked by the peripheral clock, while the other is

clocked by a fixed reference source, such as the

Timer1 oscillator.

Both timers are cleared, but the timer clocked by the

reference generates interrupts. When an interrupt

occurs, the internally clocked timer is read and both

timers are cleared. If the internally clocked timer value

is much greater than expected, then the internal

oscillator block is running too fast. To adjust for this,

decrement the OSCTUNE register.

3.6.5.3

Compensating with the CCP Module

in Capture Mode

A CCP module can use free running Timer1 (or

Timer3), clocked by the internal oscillator block and an

external event with a known period (i.e., AC power

frequency). The time of the first event is captured in the

CCPRxH:CCPRxL registers and is recorded for use

later. When the second event causes a capture, the

time of the first event is subtracted from the time of the

second event. Since the period of the external event is

known, the time difference between events can be

calculated.

If the measured time is much greater than the

calculated time, the internal oscillator block is running

too fast. To compensate, decrement the OSCTUNE

calculated time, the internal oscillator block is running

too slow. To compensate, increment the OSCTUNE

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